inside those families, devices may be unique PICnnCxxx (CMOS) or PICnnFxxx (Flash). "C" gadgets are generally categorized both "end-Of-lifestyles" (no longer available), or "not suitable for brand new development" (not actively promoted by Microchip). the program memory of "C" gadgets is variously described as OTP, ROM, or EEPROM. As of October 2016, the only OTP product labeled as "In production" is the pic16HV540. "C" devices with quartz windows (for erasure), are in fashionable not to be had.
PIC10 and PIC12
For extra details on this own family of microcontrollers, see percent training listings § Baseline middle devices (12-bit).
these gadgets characteristic a 12-bit wide code memory, a 32-byte sign up file, and a tiny two degree deep name stack. they're represented through the PIC10 collection, as well as with the aid of some PIC12 and PIC16 devices. Baseline gadgets are available in 6-pin to forty-pin packages.
generally the first 7 to nine bytes of the sign up record are unique-cause registers, and the final bytes are standard motive RAM. tips are applied the usage of a register pair: after writing an address to the FSR (file pick out sign in), the INDF (oblique f) sign in turns into an alias for the addressed check in. If banked RAM is applied, the bank number is chosen by using the high three bits of the FSR. This influences sign in numbers sixteen–31; registers 0–15 are global and now not stricken by the financial institution pick bits.
because of the very constrained check in area (five bits), 4 not often study registers had been not assigned addresses, however written via special commands (option and TRIS).
The ROM address space is 512 phrases (12 bits each), which can be prolonged to 2048 words with the aid of banking. name and GOTO instructions specify the low 9 bits of the new code area; extra high-order bits are taken from the fame sign up. word that a call preparation simplest includes eight bits of address, and can best specify addresses within the first 1/2 of each 512-phrase web page.
lookup tables are applied using a computed GOTO (venture to PCL register) right into a table of RETLW instructions.
This "baseline center" does not aid interrupts; all I/O ought to be polled. There are some "superior baseline" editions with interrupt help and a four-level call stack.
PIC10F32x gadgets feature a mid-range 14-bit extensive code reminiscence of 256 or 512 phrases, a 64-byte SRAM sign in file, and an eight-degree deep hardware stack. these devices are available in 6-pin SMD and 8-pin DIP programs (with pins unused). One enter handiest and 3 I/O pins are available. A complicated set of interrupts are available. Clocks are an inner calibrated high-frequency oscillator of sixteen MHz with a desire of selectable speeds via software and a 31 kHz low-energy source.
PIC16
For extra info on this family of microcontrollers, see p.c coaching listings § Mid-variety middle gadgets (14 bit), and p.c training listings § stronger mid-variety middle gadgets (14 bit).
those gadgets characteristic a 14-bit wide code reminiscence, and an advanced eight-stage deep call stack. The training set differs little or no from the baseline gadgets, however the additional opcode bits allow 128 registers and 2048 phrases of code to be immediately addressed. There are some additional miscellaneous instructions, and additional eight-bit literal commands, upload and subtract. The mid-variety center is available in the general public of gadgets labeled PIC12 and PIC16.
the primary 32 bytes of the sign up space are allotted to special-cause registers; the ultimate ninety six bytes are used for fashionable-reason RAM. If banked RAM is used, the excessive 16 registers (0x70–0x7F) are international, as are among the maximum vital unique-motive registers, such as the fame register which holds the RAM financial institution pick out bits. (the opposite global registers are FSR and INDF, the low eight bits of the program counter PCL, the pc high preload check in PCLATH, and the grasp interrupt control check in INTCON.)
The PCLATH check in components high-order preparation deal with bits while the 8 bits furnished through a write to the PCL check in, or the 11 bits provided by means of a GOTO or call instruction, isn't enough to cope with the to be had ROM area.
PIC17
The 17 collection never became famous and has been outmoded by means of the PIC18 architecture (however, see clones below). The 17 collection isn't always endorsed for new designs, and availability may be restrained to customers.
upgrades over in advance cores are 16-bit huge opcodes (allowing many new instructions), and a sixteen-stage deep name stack. PIC17 gadgets have been produced in applications from forty to sixty eight pins.
The 17 series added a number of essential new functions:[7]
a reminiscence mapped accumulator
read access to code reminiscence (table reads)
direct sign in to check in actions (prior cores needed to circulate registers through the accumulator)
an outside program reminiscence interface to amplify the code space
an eight-bit × 8-bit hardware multiplier
a 2nd oblique sign in pair
car-increment/decrement addressing controlled via manipulate bits in a standing sign in (ALUSTA)
A giant drawback turned into that RAM area turned into constrained to 256 bytes (26 bytes of unique feature registers, and 232 bytes of trendy-purpose RAM), with awkward financial institution-switching in the models that supported extra.
PIC18
For greater info on this own family of microcontrollers, see p.c guidance listings § PIC18 excessive cease middle devices (16 bit).
In 2000, Microchip delivered the PIC18 architecture.[3] unlike the 17 series, it has validated to be very famous, with a huge wide variety of device variations presently in manufacture. In evaluation to earlier devices, which had been more regularly than now not programmed in meeting, C has become the important improvement language.[8]
The 18 collection inherits most of the features and instructions of the 17 series, at the same time as adding a number of critical new functions:
name stack is 21 bits extensive and plenty deeper (31 stages deep)
the call stack may be read and written (TOSU:TOSH:TOSL registers)
conditional branch instructions
listed addressing mode (PLUSW)
extending the FSR registers to 12 bits, permitting them to linearly address the complete facts address area
the addition of some other FSR register (bringing the quantity up to three)
The RAM space is 12 bits, addressed the use of a four-bit financial institution pick out register and an 8-bit offset in each guidance. an extra "get entry to" bit in each instruction selects between bank zero (a=0) and the bank selected through the BSR .
A 1-stage stack is likewise available for the reputation, WREG and BSR registers. they're saved on each interrupt, and may be restored on return. If interrupts are disabled, they will additionally be used on subroutine name/return by way of setting the s bit (appending ", fast" to the education).
the car increment/decrement feature turned into stepped forward by way of casting off the manage bits and adding 4 new oblique registers according to FSR. depending on which indirect document check in is being accessed it's miles feasible to postdecrement, postincrement, or preincrement FSR; or shape the effective cope with by using adding W to FSR.
In greater superior PIC18 devices, an "extended mode" is available which makes the addressing even more favorable to compiled code:
a brand new offset addressing mode; a few addresses which have been relative to the get entry to financial institution at the moment are interpreted relative to the FSR2 check in
the addition of several new instructions, incredible for manipulating the FSR registers.
those adjustments have been by and large aimed toward improving the efficiency of a information stack implementation. If FSR2 is used either because the stack pointer or frame pointer, stack objects can be without difficulty listed – permitting extra efficient re-entrant code. Microchip's MPLAB C18 C compiler chooses to use FSR2 as a frame pointer.
