Separate code and facts areas (Harvard architecture).

A small wide variety of fixed-period instructionsmost commands are single-cycle (2 clock cycles, or four clock cycles in 8-bit models), with one put off cycle on branches and skipsOne accumulator (W0), the usage of which (as source operand) is implied (i.e. isn't encoded inside the opcode)All RAM locations feature as registers as each source and/or vacation spot of math and different capabilities.[22]A hardware stack for storing return addresses

A small quantity of addressable statistics space (32, 128, or 256 bytes, relying at the own family), prolonged thru banking

data-space mapped CPU, port, and peripheral registers

ALU fame flags are mapped into the records area

the program counter is also mapped into the information area and writable (this is used to put in force oblique jumps).

there's no distinction among reminiscence space and sign in space due to the fact the RAM serves the process of both reminiscence and registers, and the RAM is usually just known as the register file or truly as the registers.

data area (RAM)

images have a set of registers that function as widespread-motive RAM. special-motive control registers for on-chip hardware sources also are mapped into the information space. The addressability of memory varies depending on device collection, and all p.c devices have some banking mechanism to increase addressing to additional reminiscence. Later series of devices feature pass instructions, that can cover the whole addressable area, impartial of the chosen financial institution. In in advance gadgets, any check in flow had to be completed through the accumulator.

To put into effect oblique addressing, a "record pick register" (FSR) and "indirect check in" (INDF) are used. A check in variety is written to the FSR, after which reads from or writes to INDF will honestly be to or from the register pointed to via FSR. Later gadgets prolonged this idea with post- and pre- increment/decrement for greater efficiency in gaining access to sequentially stored data. This also permits FSR to be treated nearly like a stack pointer (SP).

outside statistics reminiscence is not immediately addressable besides in some PIC18 gadgets with high pin depend.

Code space

The code space is usually implemented as on-chip ROM, EPROM or flash ROM. In preferred, there may be no provision for storing code in outside memory because of the dearth of an outside reminiscence interface. The exceptions are PIC17 and pick out high pin count PIC18 devices.

word length

All pix cope with (and cope with) statistics in eight-bit chunks. but, the unit of addressability of the code area isn't commonly the same as the information area. as an instance, pics within the baseline (PIC12) and mid-range (PIC16) families have application reminiscence addressable within the identical wordsize because the education width, i.e. 12 or 14 bits respectively. In comparison, inside the PIC18 collection, the program memory is addressed in 8-bit increments (bytes), which differs from the coaching width of 16 bits.

so that you can be clear, the program reminiscence ability is generally stated in number of (single-word) instructions, instead of in bytes.

Stacks

images have a hardware name stack, that's used to save go back addresses. The hardware stack isn't always software-handy on earlier devices, however this modified with the 18 series gadgets.

hardware assist for a fashionable-reason parameter stack was lacking in early collection, but this greatly improved within the 18 series, making the 18 series structure more pleasant to high-level language compilers.